ds1000ind industrial temperature range 5-tap silicon delay line ds1000ind 021798 1/6 features ? all-silicon time delay ? 5 taps equally spaced ? delays are stable and precise ? both leading and trailing edge accuracy ? delay tolerance + 5% or + 2 ns, whichever is greater (@25 c) ? delays characterized over 40 c to +85 c tempera- ture range (+ 2 ns or + 8%) ? low-power cmos ? ttl/cmos-compatible ? vapor phase, ir and wave solderable ? custom delays available ? fast turn prototypes pin assignment 2 in nc nc tap 2 nc tap 4 gnd vcc nc tap 1 nc tap 3 nc tap 5 in tap 2 tap 4 gnd vcc tap 1 tap 3 tap 5 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1 2 3 4 8 7 6 5 ds1000mind 8-pin dip (300 mil) see mech. drawings section ds1000ind 14-pin dip (300 mil) see mech drawings section tap 2 tap 4 gnd tap 1 tap 3 tap 5 1 3 4 ds1000zind 8-pin soic (150 mil) see mech. drawings section v cc 8 7 6 5 in pin description tap 1-tap 5 - tap output number v cc - +5 volts gnd - ground nc - no connection in - input description the ds1000ind series delay lines have five equally spaced taps providing delays from 4 ns to 500 ns. these devices are offered in standard 8 and 14-pin dips that are pin-compatible with hybrid delay lines. alternatively, 8-pin soics are available to save pc board area. low cost and superior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and industry standard dip and soic packaging. in order to maintain complete pin compatibil- ity, dip packages are available with hybrid lead configu- rations. the ds1000ind series delay lines provide a nominal accuracy of 5% or 2 ns, whichever is greater. the ds1000ind 5-tap silicon delay line reproduces the input logic state at the output after a fixed delay as specified by the extension of the part number after the dash. the ds1000ind is designed to reproduce both leading and trailing edges with equal precision. each tap is capable of driving up to ten 74ls loads. dallas semiconductor can customize standard prod- ucts to meet special needs. for special requests and rapid delivery, call (214) 3714348.
ds1000ind 021798 2/6 logic diagram figure 1 20% 20% 20% 20% 20% in tap 1 tap 2 tap 3 tap 4 tap 5 ds1000ind part number delay table table 1 part # tap 1 tap 2 tap 3 tap 4 tap 5 part # nom tolerance nom tolerance nom tolerance nom tolerance nom tolerance part # ds1000 n om init t&v n om init t&v n om init t&v n om init t&v n om init t&v 20 4 2 2 8 2 2 12 2 2 16 2 2 20 2 2 25 5 2 2 10 2 2 15 2 2 20 2 2 25 2 2 30 6 2 2 12 2 2 18 2 2 24 2 2 30 2 2.4 35 7 2 2 14 2 2 21 2 2 28 2 2.2 35 2 2.8 40 8 2 2 16 2 2 24 2 2 32 2 2.6 40 2 3.2 45 9 2 2 18 2 2 27 2 2.2 36 2 2.9 45 2.3 3.6 50 10 2 2 20 2 2 30 2 2.4 40 2 3.2 50 2.5 4 60 12 2 2 24 2 2 36 2 2.9 48 2.4 3.9 60 3 4.8 75 15 2 2 30 2 2.4 45 2.3 3.6 60 3 4.8 75 3.8 6 100 20 2 2 40 2 3.2 60 3 4.8 80 4 6.4 100 5 8 125 25 2 2 50 2.5 4 75 3.8 6 100 5 8 125 6.3 10 150 30 2 2.4 60 3 4.8 90 4.5 7.2 120 6 9.6 150 7.5 12 175 35 2 2.8 70 3.5 5.6 105 5.3 8.4 140 7 11.2 175 8.8 14 200 40 2 3.2 80 4 6.4 120 6 9.6 160 8 12.8 200 10 16 250 50 2.5 4 100 5 8 150 7.5 12 200 10 16 250 12.5 20 500 100 5 8 200 10 16 300 15 24 400 20 32 500 25 40 notes: 1. initial tolerances are with respect to the nominal value at 25 c and 5v. 2. temperature tolerance is with respect to the initial delay value over a range of -40 c to 85 c, and a supply voltage range of 4.75 to 5.25v. 3. all tap delays tend to vary unidirectionally with temperature or voltage changes. for example, if tap 1 slows down, all other taps also slow down; tap3 can never be faster than tap2. 4. intermediate delay values and packaging variations are available on a custom basis. for further information, call (214) 3714348.
ds1000ind 021798 3/6 absolute maximum ratings* voltage on any pin relative to ground 1.0v to +7.0v operating temperature 40 c to +85 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds short circuit output current 50 ma for 1 second * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (40 c to +85 c; v cc = 5.0v 5%) parameter sym test condition min typ max units notes supply voltage v cc 4.75 5.00 5.25 v 5 high level input voltage v ih 2.2 v cc + 0.5 v 5 low level input voltage v il -0.5 0.8 v 5 input leakage current i i 0.0v < v i < v cc -1.0 1.0 ua active current i cc v cc = max; period= min. 35 75 ma 6, 8 high level output current i oh v cc =min. v oh =4 -1 ma low level output current i ol v cc =min. v ol =0.5 12 ma ac electrical characteristics parameter symbol min typ max units notes input pulse width t wi 40% of tap 5 t plh ns 7 input to tap delay (leading edge) t plh no tag ns 1, 2, 3, 4, 9 input to tap delay (trailing edge) t phl no tag ns 1, 2, 3, 4, 9 power-up time t pu 100 ms input period period 4 (t wi ) ns 7 capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf
ds1000ind 021798 4/6 notes: 5. all voltages are referenced to ground. 6. measured with outputs open. 7. pulse width and period specifications may be exceeded; however, accuracy may be impaired depending on application (decoupling, layout, etc.). the device will remain functional with pulse widths down to 20% of tap 5 delay, and input periods as short as 2(t wi ). 8. i cc is a function of frequency and tap 5 delay. only a -25 operating with a 40 ns period and v cc = 5.25v will have an i cc = 75 ma. for example a -100 will never exceed 30 ma, etc. 9. see atest conditionso section at the end of this data sheet. timing diagram: silicon delay line figure 2 period 1.5v 1.5v 1.5v 1.5v 2.4v 2.4v 1.5v 0.6v 0.6v in tap t fall t rise v ih v il t plh t phl t wi t wi
ds1000ind 021798 5/6 test circuit figure 3 pulse generator time interval counter device under test vhf switch control unit start tip stop tip (time interval probe) z 0 = 50 w terminology period: the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse between the 1.5v point on the leading edge and the 1.5v point on the trailing edge or the 1.5v point on the trailing edge and the 1.5v point on the leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall (input fall time): the elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. t plh (time delay, rising): the elapsed time between the 1.5v point on the leading edge of the input pulse and the 1.5v point on the leading edge of any tap output pulse. t phl (time delay, falling): the elapsed time between the 1.5v point on the trailing edge of the input pulse and the 1.5v point on the trailing edge of any tap output pulse. test setup description no tag illustrates the hardware configuration used for measuring the timing parameters on the ds1000ind. the input waveform is produced by a precision pulse generator under software control. time delays are measured by a time interval counter (20 ps resolution) connected between the input and each tap. each tap is selected and connected to the counter by a vhf switch control unit. all measurements are fully automated, with each instrument controlled by a central computer over an ieee 488 bus.
ds1000ind 021798 6/6 test conditions input : ambient temperature: 25 c 3 c supply voltage (v cc ): 5.0v 0.1v input pulse: high = 3.0v 0.1v low = 0.0v 0.1v source impedance: 50 ohm max. rise and fall time: 3.0 ns max. (measured between 0.6v and 2.4v) pulse width: 500 ns (1 m s for -500) period: 1 m s (2 m s for -500) output: each output is loaded with the equivalent of one 74f04 input gate. delay is measured at the 1.5v level on the rising and falling edge. note: above conditions are for test only and do not restrict the operation of the device under other data sheet condi- tions.
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